1. Field of the Invention
The present disclosure relates generally to microprocessor power consumption estimation and, more specifically, to power macromodeling techniques for register transfer level (RT-level) power estimation.
2. Background Art
In the modern computer and electronics age, power consumption has become a leading design constraint for microprocessors. Power consumption of a microprocessor may include, among other things, standard cell power consumption (e.g., power consumed by logic components and elements of a standard cell library), net or interconnect power consumption (e.g., power consumed by charging/discharging of capacitances of wires), and custom cell power consumption (e.g., power consumed by custom-designed blocks such as memories). To develop techniques for reducing microprocessor power consumption and optimizing microprocessor performance, it has become increasingly important to predict and measure microprocessor power consumption with high accuracy. “Power macromodeling” is known in the art to predict microprocessor power consumption early in the design cycle, e.g., at the RT-level.
As is well-known in the art of integrated circuit (IC) design, RT-level describes a level of operation of a digital circuit above the gate level. At the RT-level, a circuit is defined in terms of hardware registers and combinational logic blocks that join them such that the circuit's behavior can be described by the flow of signals among the registers and the combinational logic blocks that perform logical operations on those signals. RT-level can be expressed in hardware description languages (HDL), such as VHDL and Verilog, which can be compiled and reduced to actual gates and wirings. For example, the registers and combination logic defined in HDL can be synthesized and mapped by a logic synthesis or electronic design automation (EDA) tools directly to an equivalent hardware implementation file for field-programmable gate arrays (FPGA). As a result, modern designs for digital systems can begin at a very high level of abstraction, and later be reduced to lower-level design implementations.
Because power consumption is a critical concern for designers, it is beneficial to measure power consumption at various phases of the design cycle, including at the RT-level. Conventional RT-level power estimation techniques rely solely on switching activity and architectural simulation techniques to predict power dissipation in the design. Conventional techniques of high-level power modeling and estimation cannot account for certain factors, e.g., circuit parasitics (i.e., resistances and capacitances that dissipate power), because gate level structural representations are not available at the RT-level.